Untersuchung und Entwurf von Bluetooth-Empfängern für Ein-Chip-Lösungen

Product Description

The number of electronic devices between which data exchange is desired is steadily increasing. The Bluetooth communication standard enables the synchronization of data between mobile phones, PDAs, digital cameras, laptops and PCs without additional infrastructure. Equipping devices with a Bluetooth interface depends on additional costs, space and power consumption. The objective of this work is to determine the most suitable receiver structure for a cost-effective, highly integrated Bluetooth single-chip solution in CMOS technology. Existing receiver concepts are analyzed and the possibility of complete integration of Low-IF and Zero-IF receiver architectures is demonstrated. Architecture-specific problems, such as offset compensation in Zero-IF receivers and the effect of process tolerances on image frequency rejection in Low-IF receivers, are described and solution approaches presented. The system-level comparison of the architectures shows the suitability of both concepts and leads to parallel analysis up to the fabrication of both receivers. The relationship between the properties of individual system blocks, such as linearity and noise, on those of the receiver is discussed and the required characteristics of circuits, system blocks and receivers are explained. The system analysis results in the required properties of system blocks and specifications for circuit design. To achieve an optimal solution, various concepts and architectures for implementing the LNA, mixer and channel filter are presented. System, circuit and layout aspects are addressed to minimize interference effects associated with a single-chip solution, such as crosstalk between analog and digital system components. Based on the results, the implementation of the Low-IF receiver together with a transmitter and digital circuit components in 0.25 μm CMOS technology is finally described.